AXI (Advanced eXtensible Interface) Protocol Training

The AXI protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is a high-performance, high-frequency bus standard widely used in SoC designs. Indeeksha’s AXI Verification Training focuses on hands-on learning using SystemVerilog and UVM, equipping trainees with the skills to work on real-world chip verification projects.

What You Will Learn:

• AXI interface architecture: write, read, and response channels

• Out-of-order transactions and burst types

• AXI4, AXI4-Lite, and AXI4-Stream protocols

• AXI Stream transaction modeling and verification

• Coverage-driven verification using SystemVerilog and UVM

• Debugging and waveform analysis of AXI-based transactions

Training Modes:

• AXI Verification using SystemVerilog (SV)

• AXI Verification using UVM

• AXI Stream Verification using SV

• AXI Stream Verification using UVM

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AHB (Advanced High-performance Bus) Protocol Training

AHB, another AMBA protocol by ARM, is designed for high-speed, high-frequency communication in SoC systems. It supports burst transfers, single-cycle accesses, and split transactions. Our AHB Verification Training provides an industry-aligned approach to learn protocol-level verification using SystemVerilog and UVM.

What You Will Learn:

• AHB protocol basics: signal-level understanding and timing diagrams

• Burst, split, and pipelined transaction implementation

• Master-slave architecture in AHB systems

• Testbench creation using SV and UVM methodology

• Functional coverage and constrained-random verification

• Debugging AHB interfaces using simulation waveforms

Training Modes:

• AHB Verification using SystemVerilog (SV)

• AHB Verification using UVM